Staff Machine Learning Compiler Engineer

In this position you will be a key member of the ML Compiler team working on software tools to enable inference of deep learning networks hardware on Rivian Hardware Platforms. You will work closely with the Rivian Autonomy and Hardware teams and evaluate various implementation targeting for performance. You will help bring up new hardware and add support in the compiler for these hardware features.

This compiler enables HW-SW codesign and would result in developing efficient building blocks for state-of-the-art machine learning models. You will be collaborating with other cross functional teams in understanding the workloads, enabling running workloads on HW and help define the future enhancements to hardware and models.

• Lead the development of an ML Compiler for mapping Autonomy ML models to Rivian Autonomy Processor (RAP1).

• Design and implement hardware-aware optimizations, including quantization strategies, model compression, memory-efficient representations, and operator fusion, targeted to RAP1.

• Collaborate with hardware teams to co-optimize model architecture and compute pipeline under real-time constraints (latency, throughput, power).

• Benchmark and analyze system performance across platforms and iterate to achieve optimal deployment efficiency.

• Partner with autonomy teams to align model optimization efforts with hardware roadmap and real-world autonomy requirements.

• Ph.D. or M.S. in Computer Engineering or a related field.

• Excellent C/C++ and Python programming skills.

• Experience with various SOC platforms used for machine learning.

• Strong understanding of deep learning software models.

• Experience in compiler pipeline development preferred.

• Proficiency in deep learning frameworks and their low-level IRs or export formats.

• Experience working in aggressive design environments is preferred.

Preferred Qualifications* Prior experience working with hardware-software co-design, especially for autonomous or robotics platforms.

• Deep knowledge of numerical precision trade-offs, quantization-aware training (QAT), and dynamic/static quantization flows.
• Familiarity with embedded real-time constraints and hardware profiling/debugging tools.
• Familiarity with rearchitecting models to best suit hardware capabilities.